# HG changeset patch
# User Matt Mackall <mpm@selenic.com>
# Date 1249941526 18000
# Node ID 9360c97848b6e97b72fc429b2b4524099405f008
# Parent  6dff35c285116ab82116ddea0801d22ad93bfbd6
imported patch comcerto-100

diff -r a86b4dc28a76 arch/arm/mach-comcerto/comcerto-100.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/comcerto-100.c	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,535 @@
+/*
+ *  linux/arch/arm/mach-comcerto/comcerto-100.c
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/irq.h>
+#include <mach/map.h>
+#include <mach/time.h>
+#include <mach/comcerto-timers.h>
+#if defined(CONFIG_CACHE_L2X0)
+#include <asm/hardware/cache-l2x0.h>
+#endif
+
+#ifdef CONFIG_COMCERTO_PCI_TX_DMA_ARAM
+void aram_allocator_init(void);
+#endif
+
+struct irq_table {
+	unsigned int irq;
+	irq_flow_handler_t handle;
+	unsigned int prio;
+};
+
+extern int noirqdebug;
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/***********************************************************
+ *   Virtual address Mapping                               *
+ *                                                         *
+ ***********************************************************/
+
+static struct map_desc comcerto_io_desc[] __initdata =
+{
+	/* ARAM */
+	{ARAM_MEMORY_VADDR, __phys_to_pfn(COMCERTO_ARAM_BASE), ARAM_MEMORY_SIZE, MT_DEVICE},
+	/* SDRAM used by MSP*/
+	{SDRAM_MSP_MEMORY_VADDR, __phys_to_pfn(SDRAM_MSP_MEMORY_PHY), SDRAM_MSP_MEMORY_SIZE, MT_DEVICE},
+	
+
+	/* Block on APB bus */
+	{APB_VADDR(COMCERTO_APB_PHI_BASE), __phys_to_pfn(COMCERTO_APB_PHI_BASE), SZ_64K, MT_DEVICE},
+	{APB_VADDR(COMCERTO_APB_TIMER_BASE), __phys_to_pfn(COMCERTO_APB_TIMER_BASE), SZ_64K,	MT_DEVICE},
+	{APB_VADDR(COMCERTO_APB_GPIO_BASE), __phys_to_pfn(COMCERTO_APB_GPIO_BASE), SZ_64K, MT_DEVICE},
+	{APB_VADDR(COMCERTO_APB_UART0_BASE), __phys_to_pfn(COMCERTO_APB_UART0_BASE), SZ_16K, MT_DEVICE},	// TODO Check if can be done by driver 
+	{APB_VADDR(COMCERTO_APB_UART1_BASE), __phys_to_pfn(COMCERTO_APB_UART1_BASE), SZ_16K, MT_DEVICE},	// TODO Check if can be done by driver or Controlled by MSP 
+	{APB_VADDR(COMCERTO_APB_SPI_BASE), __phys_to_pfn(COMCERTO_APB_SPI_BASE), SZ_16K, MT_DEVICE},		// Mapped by driver
+	{APB_VADDR(COMCERTO_APB_I2C_BASE), __phys_to_pfn(COMCERTO_APB_I2C_BASE), SZ_16K, MT_DEVICE},		// Mapped by driver
+	{APB_VADDR(COMCERTO_APB_INTC_BASE), __phys_to_pfn(COMCERTO_APB_INTC_BASE), SZ_64K, MT_DEVICE},
+	{APB_VADDR(COMCERTO_APB_CLK_BASE), __phys_to_pfn(COMCERTO_APB_CLK_BASE), SZ_64K, MT_DEVICE},
+	{APB_VADDR(COMCERTO_APB_EMAC0_BASE), __phys_to_pfn(COMCERTO_APB_EMAC0_BASE), SZ_64K, MT_DEVICE},		
+	{APB_VADDR(COMCERTO_APB_EMAC1_BASE), __phys_to_pfn(COMCERTO_APB_EMAC1_BASE), SZ_64K, MT_DEVICE},		
+	{APB_VADDR(COMCERTO_APB_IDMA_BASE), __phys_to_pfn(COMCERTO_APB_IDMA_BASE), SZ_64K, MT_DEVICE},		// Mapped by EMAC driver and MSP
+	{APB_VADDR(COMCERTO_APB_EXPBUS_BASE), __phys_to_pfn(COMCERTO_APB_EXPBUS_BASE), SZ_64K, MT_DEVICE},
+	{COMCERTO_IPSEC_VADDR_BASE , __phys_to_pfn(COMCERTO_IPSEC_BASE), SZ_16M, MT_DEVICE},
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB) && !defined(CONFIG_COMCERTO_PCI_SINGLE_ACCESS_TYPE)
+	{COMCERTO_PCI_MEM_VBASE, __phys_to_pfn(COMCERTO_HIF_BASE), SZ_128M, MT_DEVICE},
+#endif
+#if defined(CONFIG_CACHE_L2X0)
+	{COMCERTO_L2CC_VADDR_BASE, __phys_to_pfn(COMCERTO_L2CC_BASE), SZ_4K, MT_DEVICE},
+#endif
+};
+
+void __init comcerto_map_io(void)
+{
+	iotable_init(comcerto_io_desc, ARRAY_SIZE(comcerto_io_desc));
+}
+
+/*
+ * We use DMA zone to allocate L1 cacheable and L2 non cacheable Ethernet buffers.
+ * Adjust zones to have x MB in DMA zone (We only allocate entire sections for
+ * the DMA ZONE).
+ */
+ void __init comcerto_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size)
+{
+	unsigned int sz = ((__pa(swapper_pg_dir) & SECTION_MASK) - PHYS_OFFSET) >> PAGE_SHIFT;
+
+	if (node || (zone_size[0] <= sz))
+		return;
+
+	zone_size[1] = zone_size[0] - sz;
+	zone_size[0] = sz;
+	zhole_size[1] = zhole_size[0];
+	zhole_size[0] = 0;
+}
+
+/***********************************************************
+ *   IRQs                                                  *
+ *                                                         *
+ ***********************************************************/
+/*********************************
+ * 
+ *********************************/
+void fastcall
+comcerto_handle_gpio_irq(unsigned int irq, struct irq_desc *desc)
+{
+	u32 pending;
+	/*
+	 * Mask IRQ.
+	 */
+	desc->chip->mask(irq);
+
+	do {
+		handle_simple_irq(irq, desc);
+		/*
+	 	* Ack IRQ.
+	 	*/
+		desc->chip->ack(irq);
+		/*
+	 	* Source interrupts are usually active low
+	 	*/
+		pending = comcerto_gpio_read(1 << ((irq - 1) % 32)) ? 0 : 1;
+
+	} while (pending);
+
+	/*
+	 * UnMask IRQ.
+	 */
+	desc->chip->unmask(irq);
+
+}
+
+void fastcall
+comcerto_handle_secondary_level_irq(unsigned int irq, struct irq_desc *desc)
+{
+	struct irqaction *action;
+	irqreturn_t action_ret;
+
+	spin_lock(&desc->lock);
+	desc->chip->mask(irq);
+
+	if (unlikely(desc->status & IRQ_INPROGRESS))
+		goto out_unlock;
+	desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+	kstat_incr_irqs_this_cpu(irq, desc);
+
+	/*
+	 * If its disabled or no action available
+	 * keep it masked and get out of here
+	 */
+	action = desc->action;
+	if (unlikely(!action || (desc->status & IRQ_DISABLED))) {
+		desc->status |= IRQ_PENDING;
+		goto out_unlock;
+	}
+
+	desc->status |= IRQ_INPROGRESS;
+	desc->status &= ~IRQ_PENDING;
+	spin_unlock(&desc->lock);
+
+	action_ret = handle_IRQ_event(irq, action);
+	if (!noirqdebug)
+		note_interrupt(irq, desc, action_ret);
+
+	spin_lock(&desc->lock);
+	desc->status &= ~IRQ_INPROGRESS;
+
+	desc->chip->ack(irq);
+
+	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
+		desc->chip->unmask(irq);
+out_unlock:
+	spin_unlock(&desc->lock);
+}
+
+
+static void comcerto_irq_mask_0(unsigned int irq)
+{
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_0) & ~(1UL << irq), COMCERTO_INTC_CSP_IRQMASK_0);
+}
+
+static void comcerto_irq_ack_0(unsigned int irq)
+{
+	__raw_writel(1UL << irq, COMCERTO_INTC_STATUS_REG_0);
+}
+
+static void comcerto_irq_mask_ack_0(unsigned int irq)
+{
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_0) & ~(1UL << irq), COMCERTO_INTC_CSP_IRQMASK_0);
+	__raw_writel(1UL << irq, COMCERTO_INTC_STATUS_REG_0);
+}
+
+static void comcerto_irq_unmask_0(unsigned int irq)
+{
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_0) | (1UL << irq), COMCERTO_INTC_CSP_IRQMASK_0);
+}
+
+static int comcerto_set_irq_type_0(unsigned int irq, unsigned int type)
+{
+	return 0;
+}
+
+static void comcerto_irq_mask_1(unsigned int irq)
+{
+	irq -= 32;
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_1) & ~(1UL << irq), COMCERTO_INTC_CSP_IRQMASK_1);
+}
+
+static void comcerto_irq_ack_1(unsigned int irq)
+{
+	irq -= 32;
+	__raw_writel(1UL << irq, COMCERTO_INTC_STATUS_REG_1);
+}
+
+static void comcerto_irq_mask_ack_1(unsigned int irq)
+{
+	irq -= 32;
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_1) & ~(1UL << irq), COMCERTO_INTC_CSP_IRQMASK_1);
+	__raw_writel(1UL << irq, COMCERTO_INTC_STATUS_REG_1);
+}
+
+static void comcerto_irq_unmask_1(unsigned int irq)
+{
+	irq -= 32;
+	__raw_writel(__raw_readl(COMCERTO_INTC_CSP_IRQMASK_1) | (1UL << irq), COMCERTO_INTC_CSP_IRQMASK_1);
+}
+
+static int comcerto_set_irq_type_1(unsigned int irq, unsigned int type)
+{
+	return 0;
+}
+
+static struct irq_chip comcerto_irq_chip_0 = { 
+	.name		= "COMCERTO100 IC0",
+	.ack		= comcerto_irq_ack_0,
+	.mask		= comcerto_irq_mask_0,
+	.unmask		= comcerto_irq_unmask_0,
+	.set_type	= comcerto_set_irq_type_0,
+	.mask_ack	= comcerto_irq_mask_ack_0,
+};
+
+static struct irq_chip comcerto_irq_chip_1 = {
+	.name		= "COMCERTO100 IC1",
+	.ack		= comcerto_irq_ack_1,
+	.mask		= comcerto_irq_mask_1,
+	.unmask		= comcerto_irq_unmask_1,
+	.set_type	= comcerto_set_irq_type_1,
+	.mask_ack	= comcerto_irq_mask_ack_1,
+};
+
+/* IRQ configuration table */
+static struct irq_table comcerto_irq_table[] __initdata =
+{
+	{STATUS_REG_1,		NULL,					0},
+	{IRQ_EDMA0RX,		handle_simple_irq,			1},
+	{IRQ_EDMA1RX,		handle_simple_irq,			2},
+	{IRQ_EDMA0TX,		handle_simple_irq,			3},
+	{IRQ_EDMA1TX,		handle_simple_irq,			4},
+	{IRQ_USB0,		comcerto_handle_secondary_level_irq,	5},
+	{IRQ_USB1,		comcerto_handle_secondary_level_irq,	6},
+	{IRQ_HIF,		comcerto_handle_secondary_level_irq,	7},
+	{IRQ_PTP0,		handle_level_irq,			8},
+	{IRQ_TIMERB,		comcerto_handle_secondary_level_irq,	9},
+	{IRQ_SPI,		comcerto_handle_secondary_level_irq,	10},
+	{IRQ_EMAC0,		comcerto_handle_secondary_level_irq,	11},
+	{IRQ_EMAC1,		comcerto_handle_secondary_level_irq,	12},
+	{IRQ_IPSEC_WRAP,	comcerto_handle_secondary_level_irq,	13},
+	{IRQ_APBB,		comcerto_handle_secondary_level_irq,	14},
+	{IRQ_I2C,		comcerto_handle_secondary_level_irq,	15},
+	{32 + IRQ_CSP_PMU,	handle_level_irq,			-1},
+	{32 + IRQ_UART1,	comcerto_handle_secondary_level_irq,	-1},
+	{32 + IRQ_UART0,	comcerto_handle_secondary_level_irq,	-1},
+	{32 + IRQ_G2,		comcerto_handle_gpio_irq,		-1},
+	{32 + IRQ_G1,		comcerto_handle_gpio_irq,		-1},
+	{32 + IRQ_G0,		comcerto_handle_gpio_irq,		-1},
+	{32 + IRQ_FPP,		handle_level_irq,			-1},
+	{32 + IRQ_VDMA1_TX,	handle_level_irq,			-1},
+	{32 + IRQ_VDMA1_RX,	handle_level_irq,			-1},
+	{32 + IRQ_VDMA0_TX,	handle_level_irq,			-1},
+	{32 + IRQ_VDMA0_RX,	handle_level_irq,			-1},
+	{32 + IRQ_TOFPP_DMA,	handle_level_irq,			-1},
+	{32 + IRQ_SPDRV_ACP_REQ,	handle_level_irq,		-1},
+	{32 + IRQ_SPDRV_ACP_WORK_DONE,	handle_level_irq,		-1}
+};
+
+
+/*********************************
+ * void comcerto_init_irq (void)
+ *
+ * Called by kernel
+ *
+ *********************************/
+void __init comcerto_init_irq (void)
+{
+	unsigned int irq, prio;
+	u32 prio_reg, prio_off, prio_mask;
+	int i;
+
+	/* Mask all interrupts */
+	__raw_writel(0, COMCERTO_INTC_CSP_IRQMASK_0);
+	__raw_writel(0, COMCERTO_INTC_CSP_IRQMASK_1);
+
+	for (i = 0; i < ARRAY_SIZE(comcerto_irq_table); i++) {
+		irq = comcerto_irq_table[i].irq;
+
+		/* setup interrupt handler and priority */
+		if (irq < 32) {
+			set_irq_chip(irq, &comcerto_irq_chip_0);
+
+			prio = comcerto_irq_table[i].prio;
+
+			prio_reg = COMCERTO_INTC_CSP_PRTY_0 + 4 * (prio / 4);
+			prio_off = ((prio % 4) << 3);
+			prio_mask = 0x1f << prio_off;
+
+			__raw_writel((__raw_readl(prio_reg) & ~prio_mask) | (irq << prio_off), prio_reg);
+		} else {
+			set_irq_chip(irq, &comcerto_irq_chip_1);
+		}
+
+		set_irq_handler(irq, comcerto_irq_table[i].handle);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+}
+
+/***********************************************************
+ *   KERNEL TIMER                                          *
+ *   (Functions called  by the kernel)                     *
+ ***********************************************************/
+
+static unsigned long systimer_mark;
+
+/*
+ * Routine to catch timer interrupts
+ */
+irqreturn_t comcerto_timer_interrupt(int irq, void *dev_id)
+{
+	u32 status;
+	u8 handled = 0;
+
+	status = __raw_readl(COMCERTO_TIMER_STATUS);
+
+	/* timer1 expired */
+	if (status & COMCERTO_TIMER1) {
+		/*Clear status*/
+		__raw_writel(COMCERTO_TIMER1, COMCERTO_TIMER_STATUS);
+
+		timer_tick();
+		systimer_mark = comcerto_timer1_get();
+		handled = 1;
+	}
+
+	/* timer2 expired */
+	else if (status & COMCERTO_TIMER2) {
+		__raw_writel(COMCERTO_TIMER2, COMCERTO_TIMER_STATUS);
+		timer_hw_handler(2);
+		handled = 1;
+	}
+
+	/* timer3 expired */
+	else if (status & COMCERTO_TIMER3) {
+		__raw_writel(COMCERTO_TIMER3, COMCERTO_TIMER_STATUS);
+		timer_hw_handler(3);
+		handled = 1;
+	}
+	if (handled)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+static struct irqaction comcerto_timer_irq = {
+	.name		= "timer",
+	.flags		= IRQF_DISABLED,
+	.handler	= comcerto_timer_interrupt,
+};
+
+
+/*
+ * Timer registration, initialisation
+ * Called by the kernel
+ */
+static void __init comcerto_timer_init(void)
+{
+	/*
+	 * DO NOT MODIFY THE CONFIGURATION OF TIMER0
+	 * It is used by the MSP
+	 */
+
+//	spin_lock_init(&timer_lock);		/*This spin lock is used to avoid concurrency when we use the others timer*/
+
+	/* Mask all the timers except timer0 */
+	comcerto_timer_disable(1);
+	comcerto_timer_disable(2);
+	comcerto_timer_disable(3);
+
+	/* Clear all the timers except timer0  */
+	__raw_writel(COMCERTO_TIMER_CSP, COMCERTO_TIMER_STATUS);
+
+	/* Register interrupt handler for interrupt on IRQ_TIMERB*/
+	setup_irq(IRQ_TIMERB, &comcerto_timer_irq);
+
+	/* Set and enable the system timer */
+	comcerto_timer1_set(COMCERTO_KERNEL_TIMER_VALUE);
+	comcerto_timer_enable(1);
+}
+
+unsigned long comcerto_gettimeoffset(void)
+{
+	unsigned long delta;
+
+	delta = comcerto_timer1_get();
+
+	delta = (delta >= systimer_mark) ? (delta - systimer_mark) : (delta + COMCERTO_KERNEL_TIMER_VALUE - systimer_mark);
+
+	return machinecycles_to_usecs(delta);
+}
+
+struct sys_timer comcerto_timer = {
+	.init		= comcerto_timer_init,
+	.offset		= comcerto_gettimeoffset,
+};
+
+
+/************************************************************************
+ *  GPIO
+ ************************************************************************/
+static __init void gpio_init(void)
+{
+	/* 
+	 * Configure each GPIO to be Output or Input
+	 * When Input, Configure to be Input, IRQ
+	 * When Input IRQ, Configure to be IRQ Rising Edge or IRQ falling Edge
+	 */
+
+	/*GPIO Output, others are input*/
+	__raw_writel(COMCERTO_OUTPUT_GPIO , COMCERTO_GPIO_OE_REG);
+
+	/*GPIO Input Rising Edge IRQ*/
+	__raw_writel(COMCERTO_IRQ_RISING_EDGE_GPIO, COMCERTO_GPIO_HI_INT_ENABLE_REG);
+	
+	/*GPIO Input Falling Edge IRQ*/
+	__raw_writel(COMCERTO_IRQ_FALLING_EDGE_GPIO, COMCERTO_GPIO_LO_INT_ENABLE_REG);
+
+	/* Are pins GPIO or pins used by another block*/
+//	__raw_writel(COMCERTO_GPIO_PIN_USAGE, COMCERTO_GPIO_IOCTRL_REG);
+}
+
+/************************************************************************
+ *  Expansion Bus
+ ************************************************************************/
+
+/*This variable is provided by the board file*/
+extern int comcerto_exp_values[5][6];
+
+static __init void exp_bus_init(void)
+{
+	int cs;
+
+	/*First, Reset the Expansion block*/
+	//__raw_writel(EXP_SW_RST, COMCERTO_EXP_SW_RST_R);
+
+	/*Clock divider configuration*/
+	//__raw_writel(COMCERTO_EXP_CLOCK_DIV_VALUE, COMCERTO_EXP_CLOCK_DIV_R);
+	
+	for (cs=0 ; cs < 5 ; cs++) {
+		//configure only enabled CS
+		if (comcerto_exp_values[cs][0] == 1) {
+			/*mode configuration*/
+			__raw_writel(comcerto_exp_values[cs][2], COMCERTO_EXP_CSx_CFG_R(cs));
+		
+			/*Chip select Segment size configuration*/
+			__raw_writel(comcerto_exp_values[cs][1], COMCERTO_EXP_CSx_SEG_R(cs));
+		
+			/*Chip select timing configuration*/
+			__raw_writel(comcerto_exp_values[cs][3], COMCERTO_EXP_CSx_TMG1_R(cs));
+			__raw_writel(comcerto_exp_values[cs][4], COMCERTO_EXP_CSx_TMG2_R(cs));
+			__raw_writel(comcerto_exp_values[cs][5], COMCERTO_EXP_CSx_TMG3_R(cs));
+		}
+	}
+
+	/*Chip Select activation*/
+	__raw_writel(COMCERTO_EXP_CS_EN_VALUE, COMCERTO_EXP_CS_EN_R);
+}
+
+void __init idma_init(void)
+{
+	/* IDMA priorities */
+	__raw_writel((IDMA_PUMM << 28) | (IDMA_MMHI << 24) | (IDMA_HIMM << 20) |
+		     (IDMA_HMB << 16) |(IDMA_MMEM1 << 12) | (IDMA_MMEM0 << 8) |
+		     (IDMA_EMMM1 << 4) | (IDMA_EMMM0 << 0), COMCERTO_IDMA_PRIORITY0_7);
+
+	__raw_writel(IDMA_MMPU, COMCERTO_IDMA_PRIORITY8);
+}
+
+
+/************************************************************************
+ *  Initialization of the device
+ ************************************************************************/
+void __init device_init(void)
+{
+	system_rev = (__raw_readl(COMCERTO_GPIO_PAD_CTRL) >> 4) & 0xf;
+
+#if defined(CONFIG_CACHE_L2X0)
+	/*L2 Cache Configuration (if needed, to check) */
+	l2x0_init((void*)COMCERTO_L2CC_VADDR_BASE, L210_AUX_CTRL_REG, 0);
+#endif
+
+	idma_init();
+
+	exp_bus_init();
+
+	gpio_init();
+
+#ifdef CONFIG_COMCERTO_PCI_TX_DMA_ARAM
+	aram_allocator_init();
+#endif
+}
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,118 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error "Do not include this directly, instead #include <mach/hardware.h>"
+#endif
+
+#ifndef __ASM_ARCH_COMCERTO100_H__
+#define __ASM_ARCH_COMCERTO100_H__
+
+#define REFCLKFREQ			24
+#ifdef CONFIG_ARCH_M822XX
+#define COMCERTO_AHBCLK			125 /* Mhz */
+#define COMCERTO_ARMCLK			150 /* Mhz */
+#else
+#define COMCERTO_AHBCLK			165 /* Mhz */
+#define COMCERTO_ARMCLK			450 /* Mhz */
+#endif
+/* PA of IO on APB bus */
+#define APB_PADDR_BASE			0x10000000
+
+
+/***** Physical address of IO on APB Bus *****/
+
+/* 0x001F0000 Reserved */
+#define COMCERTO_APB_MDMA_BASE			0x101E0000
+#define COMCERTO_APB_TDMA2_BASE			0x101D0000
+/* 0x101B0000 --> 0x101C0000 Reserved */
+#define COMCERTO_APB_EXPBUS_BASE		0x101A0000
+#define COMCERTO_APB_EMAC1_BASE			0x10190000
+/* 0x00110000 --> 0x00180000 Reserved */
+#define COMCERTO_APB_ASAAAB_BASE		0x10108000
+#define COMCERTO_APB_ASAEBUS_BASE		0x10100000
+#define COMCERTO_APB_ARAM_BASE			0x100F0000
+#define COMCERTO_APB_EDMA0_BASE			0x100E0100
+#define COMCERTO_APB_EDMA1_BASE			0x100E0300
+#define COMCERTO_APB_IDMA_BASE			0x100E0000
+#define COMCERTO_APB_EMAC0_BASE			0x100D0000
+#define COMCERTO_APB_PUI_BASE			0x100C0000
+#define COMCERTO_APB_CLK_BASE			0x100B0000
+#define COMCERTO_APB_INTC_BASE			0x100A0000
+#define COMCERTO_APB_I2C_BASE			0x1009C000
+#define COMCERTO_APB_SPI_BASE			0x10098000
+#define COMCERTO_APB_UART1_BASE			0x10094000
+#define COMCERTO_APB_UART0_BASE			0x10090000
+#define COMCERTO_APB_PUI_BASE			0x100C0000
+#define COMCERTO_APB_CLK_BASE			0x100B0000
+#define COMCERTO_APB_INTC_BASE			0x100A0000
+#define COMCERTO_APB_I2C_BASE			0x1009C000
+#define COMCERTO_APB_SPI_BASE			0x10098000
+#define COMCERTO_APB_UART1_BASE			0x10094000
+#define COMCERTO_APB_UART0_BASE			0x10090000
+/*	0x10080000 Reserved*/
+#define COMCERTO_APB_GPIO_BASE			0x10070000
+#define COMCERTO_APB_ASD_BASE			0x10060000
+#define COMCERTO_APB_TIMER_BASE			0x10050000
+#define COMCERTO_APB_ASA_ARAM_BASE		0x10048000
+#define COMCERTO_APB_ASA_DDR_BASE		0x10040000
+/*	0x10030000 Reserved*/
+#define COMCERTO_APB_TDMA_BASE			0x10020000
+#define COMCERTO_APB_PHI_BASE			0x10010000
+#define COMCERTO_APB_TDM_BASE			0x10000000
+
+/***** Physical address on AHB Bus *****/
+#define COMCERTO_AHB_USB1_BASE			0x0F800000
+#define COMCERTO_AHB_USB0_BASE			0x0F000000
+#define COMCERTO_IPSEC_BASE			0x0E000000
+#define COMCERTO_L2CC_BASE			0x0A0A0000
+
+#define COMCERTO_EXP_CS0_BASE			0x20000000
+#define COMCERTO_EXP_CS1_BASE			0x24000000
+#define COMCERTO_EXP_CS2_BASE			0x28000000
+#define COMCERTO_EXP_CS3_BASE			0x2C000000
+#define COMCERTO_EXP_CS4_BASE			0x30000000
+
+#define COMCERTO_HIF_BASE			0x40000000
+
+#define PCIBIOS_MIN_MEM				0x40000000
+#define PCIBIOS_MIN_IO				0x46000000
+
+#define pcibios_assign_all_busses()	1
+
+#include <mach/comcerto-100/hif.h>
+#include <mach/comcerto-100/idma.h>
+#include <mach/comcerto-100/clk-rst.h>
+#include <mach/comcerto-100/timer.h>
+#include <mach/comcerto-100/gpio.h>
+#include <mach/comcerto-100/exp-bus.h>
+#include <mach/comcerto-100/intr.h>
+#include <mach/comcerto-100/memory.h>
+#include <mach/comcerto-100/irqs.h>
+
+#define COMCERTO_INTC_CSP_IRQMASK_0	COMCERTO_INTC_ARM0_IRQMASK_0
+#define COMCERTO_INTC_CSP_IRQMASK_1	COMCERTO_INTC_ARM0_IRQMASK_1
+#define COMCERTO_INTC_CSP_FIQMASK_0	COMCERTO_INTC_ARM0_FIQMASK_0
+#define COMCERTO_INTC_CSP_FIQMASK_1	COMCERTO_INTC_ARM0_FIQMASK_1
+
+#define COMCERTO_INTC_CSP_IRQ_WNR	COMCERTO_INTC_ARM0_IRQ_WNR
+#define COMCERTO_INTC_CSP_PRTY_0	COMCERTO_INTC_ARM0_PRTY_0
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/clk-rst.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/clk-rst.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,98 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/clk-rst.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __CLK_H__
+#define __CLK_H__
+
+#define COMCERTO_CLK_ARM_CLK_CNTRL	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x00))
+#define COMCERTO_CLK_AHB_CLK_CNTRL	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x04))
+#define COMCERTO_CLK_PLL_STATUS		APB_VADDR((COMCERTO_APB_CLK_BASE + 0x08))
+#define COMCERTO_CLK_CLKDIV_CNTRL	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x0C))
+#define COMCERTO_CLK_TDM_CLK_CNTRL	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x10))
+#define COMCERTO_CLK_FSYNC_CNTRL	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x14))
+#define COMCERTO_CLK_CLK_PWR_DWN	APB_VADDR((COMCERTO_APB_CLK_BASE + 0x18))
+#define COMCERTO_CLK_RNG_CNTRL		APB_VADDR((COMCERTO_APB_CLK_BASE + 0x1C))
+#define COMCERTO_CLK_RNG_STATUS		APB_VADDR((COMCERTO_APB_CLK_BASE + 0x20))
+#define COMCERTO_CLK_ARM_CLK_CNTRL2 APB_VADDR((COMCERTO_APB_CLK_BASE + 0x24))
+#define COMCERTO_CLK_TDM_REF_DIV_RST APB_VADDR((COMCERTO_APB_CLK_BASE + 0x40))
+
+#define ARM_PLL_BY_CTRL			0x80000000	 
+#define ARM_AHB_BYP				0x04000000	 
+#define PLL_DISABLE					0x02000000	
+#define PLL_CLK_BYPASS				0x01000000	
+
+#define AHB_PLL_BY_CTRL				0x80000000	 
+#define DIV_BYPASS					0x40000000	 
+#define SYNC_MODE					0x20000000	 
+
+#define EPHY_CLKDIV_BYPASS			0x00200000
+#define EPHY_CLKDIV_RATIO_SHIFT	16
+#define PUI_CLKDIV_BYPASS			0x00004000	 
+#define PUI_CLKDIV_SRCCLK			0x00002000
+#define PUI_CLKDIV_RATIO_SHIFT		8
+#define PCI_CLKDIV_BYPASS			0x00000020	 
+#define PCI_CLKDIV_RATIO_SHIFT		0
+
+#define ARM0_CLK_PD				0x00200000
+#define ARM1_CLK_PD				0x00100000
+#define EPHY_CLK_PD					0x00080000
+#define TDM_CLK_PD					0x00040000
+#define PUI_CLK_PD					0x00020000
+#define PCI_CLK_PD					0x00010000
+#define MDMA_AHBCLK_PD				0x00000400
+#define I2CSPI_AHBCLK_PD				0x00000200
+#define UART_AHBCLK_PD				0x00000100
+#define IPSEC_AHBCLK_PD				0x00000080
+#define TDM_AHBCLK_PD					0x00000040
+#define USB1_AHBCLK_PD					0x00000020
+#define USB0_AHBCLK_PD					0x00000010
+#define GEMAC1_AHBCLK_PD				0x00000008
+#define GEMAC0_AHBCLK_PD				0x00000004
+#define PUI_AHBCLK_PD					0x00000002
+#define HIF_AHBCLK_PD					0x00000001
+
+#define ARM1_DIV_BP					0x00001000
+#define ARM1_DIV_VAL_SHIFT			8
+#define ARM0_DIV_BP					0x00000010
+#define ARM0_DIV_VAL_SHIFT			0
+
+#define AHBCLK_PLL_LOCK			0x00000002
+#define FCLK_PLL_LOCK				0x00000001
+
+
+
+#define COMCERTO_BLOCK_RESET_REG			APB_VADDR((COMCERTO_APB_CLK_BASE + 0x100))
+#define COMCERTO_CSP_RESET_REG				APB_VADDR((COMCERTO_APB_CLK_BASE + 0x104))
+
+#define RNG_RST						0x1000
+#define IPSEC_RST					0x0800
+#define DDR_RST						0x0400
+#define USB1_PHY_RST				0x0200
+#define USB0_PHY_RST				0x0100
+#define USB1_RST					0x0080
+#define USB0_RST					0x0040
+#define GEMAC1_RST					0x0020
+#define GEMAC0_RST					0x0010
+#define TDM_RST						0x0008
+#define PUI_RST						0x0004
+#define HIF_RST						0x0002
+#define PCI_RST						0x0001
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/exp-bus.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/exp-bus.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,80 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/exp-bus.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __COMCERTO_EXP_BUS_H__
+#define __COMCERTO_EXP_BUS_H__
+
+/***** Registers address *****/
+
+	#define COMCERTO_EXP_SW_RST_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x000)
+	#define COMCERTO_EXP_CS_EN_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x004)
+	#define COMCERTO_EXP_CSx_SEG_R(x)		APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x008 + (0x4 *x))
+	#define COMCERTO_EXP_CSx_CFG_R(x)		APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x01C + (0x4 *x))
+	#define COMCERTO_EXP_CSx_TMG1_R(x)		APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x030 + (0x4 *x))
+	#define COMCERTO_EXP_CSx_TMG2_R(x)		APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x044 + (0x4 *x))
+	#define COMCERTO_EXP_CSx_TMG3_R(x)		APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x058 + (0x4 *x))
+	#define COMCERTO_EXP_CLOCK_DIV_R			APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x06C)
+
+	#define COMCERTO_EXP_MFSM_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x100)
+	#define COMCERTO_EXP_CSFSM_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x104)
+	#define COMCERTO_EXP_WRSM_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x108)
+	#define COMCERTO_EXP_RDSM_R				APB_VADDR(COMCERTO_APB_EXPBUS_BASE + 0x10C)
+
+	
+/***** Masks *****/
+
+	/* EXP_SWRST_R register*/
+	#define EXP_SW_RST									0x00000001
+	
+	/* EXP_CS_EN_R register*/
+	#define EXP_CS4_EN									0x00000020
+	#define EXP_CS3_EN									0x00000010
+	#define EXP_CS2_EN									0x00000008
+	#define EXP_CS1_EN									0x00000004
+	#define EXP_CS0_EN									0x00000002
+	#define EXP_CLK_EN									0x00000001
+	
+	/* EXP_CSx_CFG_R register*/
+	#define EXP_RDY_EDG									0x00000800
+	#define EXP_RDY_EN									0x00000400
+	#define EXP_NAND_MODE								0x00000200
+	#define EXP_DM_MODE									0x00000100
+	#define EXP_STRB_MODE								0x00000080
+	#define EXP_ALE_MODE									0x00000040
+	#define EXP_RE_CMD_LVL								0x00000020
+	#define EXP_WE_CMD_LVL								0x00000010
+	#define EXP_CS_LEVEL									0x00000008
+	#define EXP_MEM_BUS_SIZE							0x00000006
+	#define EXP_MEM_BUS_SIZE_32						0x00000004
+	#define EXP_MEM_BUS_SIZE_16						0x00000002
+	#define EXP_MEM_BUS_SIZE_8							0x00000000
+
+	/* EXP_CSx_TMG1_R register */
+	/* EXP_CSx_TMG2_R register */
+	/* EXP_CSx_TMG3_R register */
+	
+	/* EXP_CLOCK_DIV_R register */
+	
+	/* EXP_MFSM_R register*/
+	/* EXP_CSFSM_R register*/
+	/* EXP_WRFSM_R register*/
+	/* EXP_RDFSM_R register*/
+	
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/gpio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/gpio.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,108 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/gpio.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __COMCERTO_GPIO_H__
+#define __COMCERTO_GPIO_H__
+	
+	/***** GPIO  *****/
+	#define COMCERTO_GPIO_OUTPUT_REG					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x00))	/*GPIO outputs register*/
+	#define COMCERTO_GPIO_OE_REG						APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x04))	/*GPIO Output Enable register*/
+	#define COMCERTO_GPIO_HI_INT_ENABLE_REG		APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x08))
+	#define COMCERTO_GPIO_LO_INT_ENABLE_REG		APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x0C))
+	#define COMCERTO_GPIO_INPUT_REG					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x10))	/*GPIO input register*/
+	#define COMCERTO_GPIO_APB_WS						APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x14))
+	#define COMCERTO_GPIO_SYSTEM_CONFIG				APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x1C))
+	#define COMCERTO_GPIO_MBIST						APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x20))
+	#define COMCERTO_GPIO_TDM_MUX					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x28))
+	#define COMCERTO_GPIO_ARM_ID					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x30))
+	#define COMCERTO_GPIO_PAD_CTRL					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x34))
+	#define COMCERTO_GPIO_LOCK_REG					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x38))
+	#define COMCERTO_GPIO_ARBITRER_CONF				APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x3C))
+	#define COMCERTO_GPIO_BOOTSTRAP_REG				APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x40))
+	#define COMCERTO_GPIO_IOCTRL_REG					APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x44))
+	#define COMCERTO_GPIO_USB_PHY_BIST_REG			APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x48))
+	#define COMCERTO_GPIO_GENERAL_CONTROL_REG	APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x4C))
+	#define COMCERTO_GPIO_DEVICE_ID_REG				APB_VADDR((COMCERTO_APB_GPIO_BASE + 0x50))
+		
+	#define GPIO_0											0x00000001
+	#define GPIO_1											0x00000002
+	#define GPIO_2											0x00000004
+	#define GPIO_3											0x00000008
+	#define GPIO_4											0x00000010
+	#define GPIO_5											0x00000020
+	#define GPIO_6											0x00000040
+	#define GPIO_7											0x00000080
+	#define GPIO_8											0x00000100
+	#define GPIO_9											0x00000200
+	#define GPIO_10										0x00000400
+	#define GPIO_11										0x00000800
+	#define GPIO_12										0x00001000
+	#define GPIO_13										0x00002000
+	#define GPIO_14										0x00004000
+	#define GPIO_15										0x00008000
+	#define GPIO_16										0x00010000
+	#define GPIO_17										0x00020000
+	#define GPIO_18										0x00040000
+	#define GPIO_19										0x00080000
+	#define GPIO_20										0x00100000
+	#define GPIO_21										0x00200000
+	#define GPIO_22										0x00400000
+	#define GPIO_23										0x00800000
+	#define GPIO_24										0x01000000
+	#define GPIO_25										0x02000000
+	#define GPIO_26										0x04000000
+	#define GPIO_27										0x08000000
+	#define GPIO_28										0x10000000
+	#define GPIO_29										0x20000000
+	#define GPIO_30										0x40000000
+	#define GPIO_31										0x80000000
+
+	/*IO Control register values*/
+	#define HBMODE_SW									0x00000400
+	#define SPI_BUS										0x00000200
+	#define UART1_BUS									0x00000100
+	#define UART0_BUS									0x00000080
+	#define I2C_BUS										0x00000040
+	#define GPBT3										0x00000020
+	#define TIMER_EVENT1								0x00000010
+	#define TIMER_EVENT0								0x00000008
+	#define EXP_BUS_A19_A21								0x00000004
+	#define EXP_BUS_A17_A18								0x00000002
+	#define EXP_BUS_A15_A16								0x00000001
+
+	/* system config status register values */
+
+	#define BOND_DEVTYP				0x00020000
+	#define BOND_VOCCH					0x00018000
+	#define PCI_HOST					0x00001000
+	#define PCI_EN						0x00000400
+	#define PLL_MODE					0x00001800
+	#define BURNIN						0x00000400
+	#define HBUSSIZE_OUT				0x00000300
+	#define TDM_CK_OUT_EN				0x00000080
+	#define SELFTEST					 	0x00000040
+	#define TM_MII1					 	0x00000030
+	#define TM_MII0					 	0x0000000C
+	#define BOOT_OP1				 	0x00000002
+	#define BOOT_OP0				 	0x00000001
+
+	#define PCI_HOST_ENABLED			(PCI_HOST | PCI_EN)
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/hif.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/hif.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,103 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/hif.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __HIF_H__
+#define __HIF_H__
+	
+	/* Virtual address of Host Interface Registers*/
+	#define COMCERTO_PHI_APB_FIFO_CONTROL			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0000))
+	#define COMCERTO_PHI_APB_FIFO_STATUS			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0004))
+	#define COMCERTO_PHI_APB_FIFO_INTACK			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0004))
+	#define COMCERTO_PHI_APB_BIST_CTRL_STAT		APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0008))
+	#define COMCERTO_PHI_APB_TX_FIFO_SIZE			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0014))
+	#define COMCERTO_PHI_APB_TX_FIFO_HI_THRESH	APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0018))
+	#define COMCERTO_PHI_APB_TX_FIFO_LO_THRESH	APB_VADDR((COMCERTO_APB_PHI_BASE + 0x001C))
+	#define COMCERTO_PHI_APB_RX_FIFO_SIZE			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0024))
+	#define COMCERTO_PHI_APB_RX_FIFO_HI_THRESH	APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0028))
+	#define COMCERTO_PHI_APB_RX_FIFO_LO_THRESH	APB_VADDR((COMCERTO_APB_PHI_BASE + 0x002C))
+	#define COMCERTO_PHI_TX_MAIL0						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0030))
+	#define COMCERTO_PHI_TX_MAIL1						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0034))
+	#define COMCERTO_PHI_TX_MAIL2						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0038))
+	#define COMCERTO_PHI_TX_MAIL3						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x003C))
+	#define COMCERTO_PHI_RX_MAIL0						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0040))
+	#define COMCERTO_PHI_RX_MAIL1						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0044))
+	#define COMCERTO_PHI_RX_MAIL2						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0048))
+	#define COMCERTO_PHI_RX_MAIL3						APB_VADDR((COMCERTO_APB_PHI_BASE + 0x004C))
+	#define COMCERTO_PHI_PCI_IF_CONTROL				APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0050))
+	#define COMCERTO_PHI_PCI_IF_STATUS				APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0054))
+	#define COMCERTO_PHI_BME_DMA_START_ADDR		APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0060))
+	#define COMCERTO_PHI_BME_DMA_BURST_SIZE		APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0064))
+	#define COMCERTO_PHI_BME_DMA_XFER_LEN			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0068))
+
+        #define COMCERTO_APBB_INT_CONTROL		APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0100))
+        #define COMCERTO_APBB_INT_STATUS		APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0104))
+        #define COMCERTO_APBB_CONTROL		        APB_VADDR((COMCERTO_APB_PHI_BASE + 0x0108))
+
+	#define COMCERTO_PHI_APB_FIFO_DATA_U8			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x4000))
+	#define COMCERTO_PHI_APB_FIFO_DATA_U16			APB_VADDR((COMCERTO_APB_PHI_BASE + 0x8000))
+	#define COMCERTO_PHI_APB_FIFO_DATA_U32			APB_VADDR((COMCERTO_APB_PHI_BASE + 0xC000))
+	/* Host Memory Bridge */
+	#define COMCERTO_HMB_FIFO_CONTROL				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xD000))
+	#define COMCERTO_HMB_HCSM_BIST_CONTROL			APB_VADDR((COMCERTO_APB_PHI_BASE + 0xD008))
+	#define COMCERTO_HMB_FIFO_DATA_U8				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xE000))
+	#define COMCERTO_HMB_FIFO_DATA_U16				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xE100))
+	#define COMCERTO_HMB_FIFO_DATA_U32				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xE200))
+	#define COMCERTO_HMB_STATE_CONTROL				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF000))
+	#define COMCERTO_HMB_MODE_CONTROL				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF004))
+	#define COMCERTO_HMB_STATUS						APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF008))
+	#define COMCERTO_HMB_INTACK						APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF008))
+	#define COMCERTO_HMB_INT_CONTROL					APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF00C))
+	#define COMCERTO_HMB_PCI_BASE_ADDR1				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF010))
+	#define COMCERTO_HMB_SYS_BASE_ADDR1				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF014))
+	#define COMCERTO_HMB_SIZE_MASK1					APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF018))
+	#define COMCERTO_HMB_PCI_BASE_ADDR2				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF020))
+	#define COMCERTO_HMB_SYS_BASE_ADDR2				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF024))
+	#define COMCERTO_HMB_SIZE_MASK2					APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF028))
+	#define COMCERTO_HMB_AX_FIFO_DEPTH				APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF030))
+	#define COMCERTO_HMB_AX_FIFO_DATA_ADDR			APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF034))
+	#define COMCERTO_HMB_AX_FIFO_DATA_LEN			APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF038))
+	#define COMCERTO_HMB_PCI_ARBITER_CONTROL		APB_VADDR((COMCERTO_APB_PHI_BASE + 0xF040))
+
+	#define PCI_DEV_VENDOR_ID				0x015018DC
+
+#define BME_RXTRGABRT		0x0080000
+#define BME_MSTRABRT		0x0100000
+#define BME_SYSERROR		0x0200000
+#define BME_PARERROR		0x0400000
+#define BME_RETRY		0x0800000
+
+#define BME_RXTRGABRTIAK	0x008
+#define BME_MSTRABRTIAK		0x010
+#define BME_SYSERRORIAK		0x020
+#define BME_PARERRORIAK		0x040
+#define BME_RETRYIAK		0x100
+
+#define TXFF_RES		0x1000
+#define RXFF_RES		0x2000
+
+#define APBB_CTRL_MEMIO		0x8
+#define APBB_CTRL_LATTMR	0x4
+#define APBB_CTRL_REQLAST	0x2
+#define APBB_CTRL_EN		0x1
+
+#define FLUSH_RX	0x80
+#define MAX_RETRY_TIMEOUT_US	10
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/idma.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/idma.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,82 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/idma.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __IDMA_H__
+#define __IDMA_H__
+
+#define COMCERTO_HDMA_SOFTRESET			APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0000)
+
+#define COMCERTO_MMHI_DMA_ENABLE		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x000C)
+#define COMCERTO_HIMM_DMA_ENABLE		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0010)
+
+#define COMCERTO_MMHI_BASE_ADDR			APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0040)
+#define COMCERTO_HIMM_BASE_ADDR			APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0044)
+
+#define COMCERTO_MMHI_BLOCK_SIZE		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0048)
+#define COMCERTO_HIMM_BLOCK_SIZE		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x004C)
+
+#define COMCERTO_HI_LOCKED_TRANSFER_SIZE	APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0050)
+
+#define COMCERTO_IDMA_PRIORITY0_7		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0060)
+#define COMCERTO_IDMA_PRIORITY8			APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0064)
+
+#define COMCERTO_HMDMA_SOFTRESET		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0070)
+#define COMCERTO_HMDMA_STATUS_OUTPUT		APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0070)
+#define COMCERTO_HMDMA_LOCKED_TRANSFER_SIZE	APB_VADDR(COMCERTO_APB_IDMA_BASE + 0x0074)
+
+
+#define IDMA_FSTATUS_FRAME_DONE_MASK	        0x80000000
+#define IDMA_FSTATUS_STATUS_MASK		0x03FFFFFF
+#define IDMA_FSTATUS_STATUS_GOOD		0x00000400
+
+#define IDMA_FCONTROL_PHY_NB_MASK		0x00000070
+#define IDMA_FCONTROL_PHY_OFFSET		0x00000004
+
+#define IDMA_FCONTROL_SCATTER			0x00000008
+#define IDMA_FCONTROL_IRQEN			0x00000004
+#define IDMA_FCONTROL_FLAST			0x00000002
+#define IDMA_FCONTROL_FREADY			0x00000001
+#define IDMA_FCONTROL_IPSEC_OUT		0x00000010
+#define IDMA_FCONTROL_IPSEC_IN			0x00000020
+
+
+
+#define IDMA_BCONTROL_BLAST			0x00010000
+#define IDMA_BCONTROL_BLEN_MASK			0x0000FFFF
+#define IDMA_BCONTROL_SCATTER_BLAST		0x80000000
+
+#define IDMA_START				0x00000001
+#define IDMA_BURST_MASK			        0x000000FF
+#define IDMA_PRTY_MASK			        0x00000700
+
+#define	FDESC_ALIGN_BYTES		0x10	
+
+/* IDMA masters */
+#define IDMA_EMMM0	0
+#define IDMA_MMEM0	1
+#define IDMA_PUMM	2
+#define IDMA_MMPU	3
+#define IDMA_HIMM	4
+#define IDMA_MMHI	5
+#define IDMA_EMMM1	6
+#define IDMA_MMEM1	7
+#define IDMA_HMB	8
+
+#endif /* __IDMA_H__ */
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/intr.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/intr.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,78 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/intr.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTINTCULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __INTR__H__
+#define __INTR__H__
+
+	/*  Comcerto Interrupt Controller */
+	#define COMCERTO_INTC_STATUS_REG_0				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x00))
+	#define COMCERTO_INTC_SET_STATUS_REG_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x04))
+	#define COMCERTO_INTC_ARM0_IRQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x08))
+	#define COMCERTO_INTC_ARM0_FIQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x0C))
+	#define COMCERTO_INTC_ARM1_IRQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x10))
+	#define COMCERTO_INTC_ARM1_FIQMASK_0			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x14))
+	
+	#define COMCERTO_INTC_ARM1_CONTROL_REG			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x18))
+	#define COMCERTO_INTC_IRQ_ACK_TEST_REG			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x1C))
+	
+	#define COMCERTO_INTC_STATUS_REG_1				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x20))
+	#define COMCERTO_INTC_SET_STATUS_REG_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x24))
+	#define COMCERTO_INTC_ARM0_IRQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x28))
+	#define COMCERTO_INTC_ARM0_FIQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x2C))
+	#define COMCERTO_INTC_ARM1_IRQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x30))
+	#define COMCERTO_INTC_ARM1_FIQMASK_1			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x34))
+	
+	#define COMCERTO_INTC_STATUS_MASK_REG_1		APB_VADDR((COMCERTO_APB_INTC_BASE + 0x38))
+	
+	#define COMCERTO_INTC_ARM0_PRTY_0				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x40))
+	#define COMCERTO_INTC_ARM0_PRTY_1				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x44))
+	#define COMCERTO_INTC_ARM0_PRTY_2				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x48))
+	#define COMCERTO_INTC_ARM0_PRTY_3				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x4C))
+	#define COMCERTO_INTC_ARM0_PRTY_4				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x50))
+	#define COMCERTO_INTC_ARM0_PRTY_5				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x54))
+	#define COMCERTO_INTC_ARM0_PRTY_6				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x58))
+	#define COMCERTO_INTC_ARM0_PRTY_7				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x5C))
+	
+	#define COMCERTO_INTC_ARM0_IRQ_WNR				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x60))
+	#define COMCERTO_INTC_ARM0_SELFCLEAR			APB_VADDR((COMCERTO_APB_INTC_BASE + 0x64))
+	#define COMCERTO_INTC_FIQ_PRTY_EN				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x68))
+	
+	#define COMCERTO_INTC_TDMA_STS					APB_VADDR((COMCERTO_APB_INTC_BASE + 0x70))
+	#define COMCERTO_INTC_TDMA_CTRL					APB_VADDR((COMCERTO_APB_INTC_BASE + 0x74))
+	#define COMCERTO_INTC_TDMA_SET					APB_VADDR((COMCERTO_APB_INTC_BASE + 0x78))
+	
+	#define COMCERTO_INTC_ARM1_PRTY_0				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x80))
+	#define COMCERTO_INTC_ARM1_PRTY_1				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x84))
+	#define COMCERTO_INTC_ARM1_PRTY_2				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x88))
+	#define COMCERTO_INTC_ARM1_PRTY_3				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x8C))
+	#define COMCERTO_INTC_ARM1_PRTY_4				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x90))
+	#define COMCERTO_INTC_ARM1_PRTY_5				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x94))
+	#define COMCERTO_INTC_ARM1_PRTY_6				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x98))
+	#define COMCERTO_INTC_ARM1_PRTY_7				APB_VADDR((COMCERTO_APB_INTC_BASE + 0x9C))
+	
+	#define COMCERTO_INTC_ARM1_IRQ_WNR				APB_VADDR((COMCERTO_APB_INTC_BASE + 0xA0))
+
+	#define COMCERTO_INTC_ARM0_IRQ_WNR_VBA			APB_VADDR((COMCERTO_APB_INTC_BASE + 0xB0))
+	#define COMCERTO_INTC_ARM1_IRQ_WNR_VBA			APB_VADDR((COMCERTO_APB_INTC_BASE + 0xB4))
+	
+	#define COMCERTO_INTC_ARM0_STS_VEC_ADDR(nb)	APB_VADDR((COMCERTO_APB_INTC_BASE + 0x100 + 4nb)))
+	#define COMCERTO_INTC_ARM1_STS_VEC_ADDR(nb)	APB_VADDR((COMCERTO_APB_INTC_BASE + 0x180 + 4nb)))
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/irqs.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/irqs.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,93 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/irqs.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __COMCERTO_IRQS_H__
+#define __COMCERTO_IRQS_H__
+
+		/* 32 First IRQs*/
+	#define IRQ_TIMERA				31				/* This IRQ is used only by the MSP */
+	#define IRQ_TIMERB				30				/* This IRQ is used only by the CSP */
+/*	#define IRQ_Reserved				29
+	#define IRQ_Reserved				28*/
+	#define IRQ_MDMA_DONE			27
+	#define IRQ_EDMA1TX				26
+	#define IRQ_EDMA1RX				25
+/*	#define IRQ_Reserved				24*/
+	#define IRQ_IPSEC_WRAP			23
+	#define IRQ_DDRC					22
+	#define IRQ_APBB					21
+	#define IRQ_EDMA0TX				20
+	#define IRQ_EDMA0RX				19
+	#define IRQ_HITXFUL				18
+	#define IRQ_HIF_RXEMT			17
+	#define IRQ_HIF					16
+	#define IRQ_TDM_TIMER			15
+	#define IRQ_SPI					14
+	#define IRQ_USB1					13
+	#define IRQ_EMAC1					12
+	#define IRQ_USB0					11
+	#define IRQ_I2C					10
+	#define IRQ_IPSEC					9
+	#define IRQ_TDMA1					8
+	#define IRQ_PUDMATX				7
+	#define IRQ_PUDMARX				6
+	#define IRQ_PUI					5
+	#define IRQ_EMAC0					4
+	#define IRQ_PTP2					3
+	#define IRQ_PTP1					2
+	#define IRQ_PTP0					1
+	#define STATUS_REG_1				0
+	
+	/* 32 next IRQs*/
+	#define IRQ_MDMA_AHB_ERR		31
+	#define IRQ_IDMA_TX_AHB_ERR	30
+	#define IRQ_IDMA_RX_AHB_ERR	29
+	#define IRQ_TDMA_TX_AHB_ERR	28
+	#define IRQ_TDMA_RX_AHB_ERR	27
+	#define IRQ_UART1					26
+	#define IRQ_FPP					25
+	#define IRQ_VDMA1_TX				24
+	#define IRQ_VDMA1_RX				23
+	#define IRQ_VDMA0_TX				22
+	#define IRQ_VDMA0_RX				21
+/*	#define IRQ_Reserved				20
+	#define IRQ_Reserved				19*/
+	#define IRQ_MSP_PMU				18
+	#define IRQ_CSP_PMU				17
+	#define IRQ_L2_PARRT				16
+	#define IRQ_L2_PARRD				15
+	#define IRQ_L2_BWABT				14
+	#define IRQ_SPDRV_ACP_REQ			13
+	#define IRQ_SPDRV_ACP_WORK_DONE			12 
+	#define IRQ_TOFPP_DMA				11
+	#define IRQ_TDMA0					10
+	#define IRQ_UART0					9
+	#define IRQ_G7						8
+	#define IRQ_G6						7
+	#define IRQ_G5						6
+	#define IRQ_G4						5
+	#define IRQ_G3						4
+	#define IRQ_G2						3
+	#define IRQ_G1						2
+	#define IRQ_G0						1
+	#define STATUS_REG_0				0
+
+	#define NR_IRQS					64
+
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/memory.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/memory.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,64 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/memory.h
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+#ifndef __MEMORY_H__
+#define __MEMORY_H__
+
+	/* Physical addresses of memories */
+	#define COMCERTO_SDRAM_BASE				0x80800000
+	#define COMCERTO_ARAM_BASE				0x0A000000
+	#define COMCERTO_ERAM_BASE				0x08000000
+	#define COMCERTO_IRAM_BASE				0x09000000
+
+	#define ARAM_MEMORY_SIZE				SZ_64K
+
+	#define SDRAM_MSP_MEMORY_PHY			0x80000000
+	#define SDRAM_MSP_MEMORY_SIZE			SZ_8M
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#define COMCERTO_PCIDMA_SIZE1		0x40000000 /* 1 GiB */
+#define COMCERTO_PCIDMA_SIZE_MASK1	(~(COMCERTO_PCIDMA_SIZE1 - 1))
+#define COMCERTO_PCIDMA_SYS_BASE_ADDR1	0x80000000 /* Must cover all physical memory and be aligned on PCIDMA_SIZE */
+#define COMCERTO_PCIDMA_PCI_BASE_ADDR1	0x80000000 /* Must be aligned on PCIDMA_SIZE and should not overlap with PCI IO and PCI MEM */
+
+#define COMCERTO_PCIDMA_SIZE2		ARAM_MEMORY_SIZE /* 64KiB */
+#define COMCERTO_PCIDMA_SIZE_MASK2	(~(COMCERTO_PCIDMA_SIZE2 - 1))
+#define COMCERTO_PCIDMA_SYS_BASE_ADDR2	COMCERTO_ARAM_BASE
+#define COMCERTO_PCIDMA_PCI_BASE_ADDR2	COMCERTO_ARAM_BASE
+
+
+
+#define __virt_to_bus(x)	__virt_to_phys(x)
+#define __bus_to_virt(x)	__phys_to_virt(x)
+
+#define msp_to_virt(p)					(void*) ((unsigned long)p - SDRAM_MSP_MEMORY_PHY + SDRAM_MSP_MEMORY_VADDR)
+#define virt_to_msp(v)					((unsigned long)v + SDRAM_MSP_MEMORY_PHY - SDRAM_MSP_MEMORY_VADDR)
+
+#define aram_to_virt(p) (void*)(((unsigned long)p - COMCERTO_ARAM_BASE) + ARAM_MEMORY_VADDR)
+#define virt_to_aram(v) (((unsigned long)v - ARAM_MEMORY_VADDR) + COMCERTO_ARAM_BASE)
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/include/mach/comcerto-100/timer.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/include/mach/comcerto-100/timer.h	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,58 @@
+/*
+ *  linux/include/asm-arm/arch-comcerto/comcerto-100/timer.h
+ *
+ *  Copyright (C) 2006 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+	/* Comcerto Timers  */
+	#define COMCERTO_TIMER0_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x00)
+	#define COMCERTO_TIMER0_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x04)
+	#define COMCERTO_TIMER1_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x08)
+	#define COMCERTO_TIMER1_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x0C)
+	#define COMCERTO_TIMER2_LOW_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x10)
+	#define COMCERTO_TIMER2_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x14)
+	#define COMCERTO_TIMER2_CTRL				APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x18)
+	#define COMCERTO_TIMER2_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x1C)
+	#define COMCERTO_TIMER3_LOW_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x20)
+	#define COMCERTO_TIMER3_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x24)
+	#define COMCERTO_TIMER3_CTRL				APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x28)
+	#define COMCERTO_TIMER3_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x2C)
+	#define COMCERTO_TIMER4_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x30)
+	#define COMCERTO_TIMER4_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x34)
+	#define COMCERTO_TIMER5_LOW_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x38)
+	#define COMCERTO_TIMER5_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x3C)
+	#define COMCERTO_TIMER5_CURRENT_COUNT			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x40)
+	#define COMCERTO_TIMER5_CTRL				APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x44)
+	#define COMCERTO_TIMER_IRQ_MASK				APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x48)
+	#define COMCERTO_TIMER_STATUS				APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x50)
+/*	#define COMCERTO_TIMER_STATUS_CLR			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0x50)*/
+	#define COMCERTO_TIMER_WDT_HIGH_BOUND			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0xD0)
+	#define COMCERTO_TIMER_WDT_CONTROL			APB_VADDR(COMCERTO_APB_TIMER_BASE + 0xD4)
+
+	/*COMCERTO_TIMER_IRQ_MASK*/
+	#define COMCERTO_TIMER0								0x01
+	#define COMCERTO_TIMER1								0x02
+	#define COMCERTO_TIMER2								0x04
+	#define COMCERTO_TIMER3								0x08
+	#define COMCERTO_TIMER4								0x10
+	#define COMCERTO_TIMER5								0x20
+	#define COMCERTO_ALL									0xFF
+	#define COMCERTO_TIMER_CSP							0x0E
+#endif
diff -r a86b4dc28a76 arch/arm/mach-comcerto/pci-comcerto100.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/arch/arm/mach-comcerto/pci-comcerto100.c	Fri Aug 14 13:45:38 2009 -0500
@@ -0,0 +1,650 @@
+/*
+ *  linux/arch/arm/mach-comcerto/pci-comcerto100.c
+ *
+ *  Copyright (C) 2004,2005 Mindspeed Technologies, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <asm/delay.h>
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/pci.h>
+#include <mach/irq.h>
+
+#define APBB_CTRL_DEFAULT	(APBB_CTRL_LATTMR | APBB_CTRL_REQLAST | APBB_CTRL_EN)
+
+#define MAX_BURST_LEN	16
+
+extern spinlock_t comcerto_pci_lock;
+
+extern void __comcerto_pci_host_init(void);
+extern  int __comcerto_host_read_config(int where, int size, u32 *value);
+
+#if !defined(CONFIG_COMCERTO_PCI_USE_APBB)
+int __comcerto_pci_check(int rx);
+#endif
+
+
+#if !defined(CONFIG_COMCERTO_PCI_SINGLE_ACCESS_TYPE)
+/**
+ * comcerto_pci_read -
+ *
+ */
+void comcerto_pci_read(u32 addr, int size, u8 *buf, u8 space_type)
+{
+	unsigned long flags;
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+	BUG();
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#else
+	
+	u32 burst = (size + 3) / 4;
+	int rc;
+
+//	printk (KERN_DEBUG "read: addr: %#x, size: %#x, type: %#x\n", addr, size, space_type);
+	if (burst > MAX_BURST_LEN)
+		burst = MAX_BURST_LEN;
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(size, COMCERTO_PHI_BME_DMA_XFER_LEN);		/* load length in bytes */
+	__raw_writel(burst, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001E, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001F, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	rc = __comcerto_pci_check(1);
+	if (!rc) {
+		do {
+			if (size >= 4) {
+				*((u32 *)buf) = __raw_readl(COMCERTO_PHI_APB_FIFO_DATA_U32);
+				buf += 4;
+				size -= 4;
+			} else if (size >= 2) {
+				*((u16 *)buf) = __raw_readw(COMCERTO_PHI_APB_FIFO_DATA_U16);
+				buf += 2;
+				size -= 2;
+			} else if (size >= 1) {
+				*buf = __raw_readb(COMCERTO_PHI_APB_FIFO_DATA_U8);
+				buf++;
+				size--;
+			}
+		} while (size);
+	} else
+		printk (KERN_ERR "read: addr: %#x, size: %#x, type: %#x\n", addr, size, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_read);
+
+
+/**
+ * comcerto_pci_readl -
+ *
+ */
+u32 comcerto_pci_readl(u32 addr, u8 space_type)
+{
+	unsigned long flags;
+	u32 value = 0;
+
+//	printk (KERN_DEBUG "readl: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	value = __raw_readl(addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#else
+	int rc;
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(4, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);			/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001E, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001F, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	rc = __comcerto_pci_check(1);
+	if (!rc)
+		value = __raw_readl(COMCERTO_PHI_APB_FIFO_DATA_U32);
+	else
+		printk (KERN_ERR "readl: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_readl);
+
+/**
+ * comcerto_pci_readw -
+ *
+ */
+u16 comcerto_pci_readw(u32 addr, u8 space_type)
+{
+	unsigned long flags;
+	u16 value = 0;
+
+//	printk (KERN_DEBUG "readw: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	value = __raw_readw(addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#else	
+	int rc;
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(2, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001E, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001F, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	rc = __comcerto_pci_check(1);
+	if (!rc)
+		value = __raw_readw(COMCERTO_PHI_APB_FIFO_DATA_U16);
+	else
+		printk (KERN_ERR "readw: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_readw);
+
+/**
+ * comcerto_pci_readb -
+ *
+ */
+u8 comcerto_pci_readb(u32 addr, u8 space_type)
+{
+	unsigned long flags;
+	u8 value = 0;
+
+//	printk (KERN_DEBUG "readb: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	value = __raw_readb(addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#else
+	int rc;
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);			/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001E, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001F, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	rc = __comcerto_pci_check(1);
+	if (!rc)
+		value = __raw_readb(COMCERTO_PHI_APB_FIFO_DATA_U8);
+	else
+		printk (KERN_ERR "readb: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+
+	return value;
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_readb);
+
+/**
+ * comcerto_pci_write -
+ *
+ */
+void comcerto_pci_write(u32 addr, int size, u8 *buf, u8 space_type)
+{
+	unsigned long flags;
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+	BUG();
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#else
+	int size_tmp = size;
+	u32 burst = (size + 3) / 4;
+	
+//	printk (KERN_DEBUG "write: addr: %#x, size: %#x, type: %#x\n", addr, size, space_type);
+
+	if (burst > MAX_BURST_LEN)
+		burst = MAX_BURST_LEN;
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	do {
+		if (size >= 4) {
+			__raw_writel(*((u32 *)buf), COMCERTO_PHI_APB_FIFO_DATA_U32);
+			buf += 4;
+			size -= 4;
+		} else if (size >= 2) {
+			__raw_writew(*((u16 *)buf), COMCERTO_PHI_APB_FIFO_DATA_U16);
+			buf += 2;
+			size -= 2;
+		} else if (size >= 1) {
+			__raw_writeb(*buf, COMCERTO_PHI_APB_FIFO_DATA_U8);
+			buf++;
+			size--;
+		}
+	} while (size);
+
+	__raw_writel(FLUSH_RX, COMCERTO_PHI_APB_FIFO_INTACK);		/* flush out the value */
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(size_tmp, COMCERTO_PHI_BME_DMA_XFER_LEN);		/* load length in bytes */
+	__raw_writel(burst, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001A, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001B, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	if (__comcerto_pci_check(0))
+		printk (KERN_ERR "write: addr: %#x, size: %#x, type: %#x\n", addr, size_tmp, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_write);
+
+/**
+ * comcerto_pci_writeb -
+ *
+ */
+void comcerto_pci_writeb(u32 addr, u8 value, u8 space_type)
+{
+	unsigned long flags;
+
+//	printk (KERN_DEBUG "writeb: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	__raw_writeb(value, addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#else
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writeb(value, COMCERTO_PHI_APB_FIFO_DATA_U8);
+
+	__raw_writel(FLUSH_RX, COMCERTO_PHI_APB_FIFO_INTACK);		/* flush out the value */
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001A, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001B, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	if (__comcerto_pci_check(0))
+		printk (KERN_ERR "writeb: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_writeb);
+
+/**
+ * comcerto_pci_writew -
+ *
+ */
+void comcerto_pci_writew(u32 addr, u16 value, u8 space_type)
+{
+	unsigned long flags;
+
+//	printk (KERN_DEBUG "writew: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	__raw_writew(value, addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#else
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writew(value, COMCERTO_PHI_APB_FIFO_DATA_U16);
+
+	__raw_writel(FLUSH_RX, COMCERTO_PHI_APB_FIFO_INTACK);		/* flush out the value */
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(2, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001A, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001B, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	if (__comcerto_pci_check(0))
+		printk (KERN_ERR "writew: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_writew);
+
+/**
+ * comcerto_pci_writel -
+ *
+ */
+void comcerto_pci_writel(u32 addr, u32 value, u8 space_type)
+{
+	unsigned long flags;
+
+//	printk (KERN_DEBUG "writel: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(APBB_CTRL_DEFAULT, COMCERTO_APBB_CONTROL);
+	else
+		__raw_writel(APBB_CTRL_DEFAULT | APBB_CTRL_MEMIO, COMCERTO_APBB_CONTROL);
+
+	__raw_writel(value, addr);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#else
+
+	spin_lock_irqsave(&comcerto_pci_lock, flags);
+
+	__raw_writel(value, COMCERTO_PHI_APB_FIFO_DATA_U32);
+
+	__raw_writel(FLUSH_RX, COMCERTO_PHI_APB_FIFO_INTACK);		/* flush out the value */
+	__raw_writel(addr, COMCERTO_PHI_BME_DMA_START_ADDR);		/* load destination of value */
+	__raw_writel(4, COMCERTO_PHI_BME_DMA_XFER_LEN);			/* load length in bytes */
+	__raw_writel(1, COMCERTO_PHI_BME_DMA_BURST_SIZE);		/* burst length in PCI data cycles, i.e, 32 bits */
+
+	/* initiate PCI dma */
+	if (space_type == PCI_SPACE_TYPE_IO)
+		__raw_writel(0x0001A, COMCERTO_PHI_PCI_IF_CONTROL);
+	else
+		__raw_writel(0x0001B, COMCERTO_PHI_PCI_IF_CONTROL);
+
+	if (__comcerto_pci_check(0))
+		printk (KERN_ERR "writel: addr: %#x, value: %#x, type: %#x\n", addr, value, space_type);
+
+	spin_unlock_irqrestore(&comcerto_pci_lock, flags);
+#endif
+}
+
+EXPORT_SYMBOL(comcerto_pci_writel);
+
+#endif /* !defined(CONFIG_COMCERTO_PCI_SINGLE_ACCESS_TYPE) */
+
+#if defined(CONFIG_COMCERTO_PCI_DEBUG)
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+static irqreturn_t comcerto_pci_apbb_irq(int irq, void *dev_id)
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+static irqreturn_t comcerto_pci_apbb_irq(int irq, void *dev_id, struct pt_regs *regs)
+#else
+static void comcerto_pci_apbb_irq(int irq, void *dev_id, struct pt_regs *regs)
+#endif
+{
+	u32 status;
+
+	status = __raw_readl(COMCERTO_APBB_INT_STATUS);
+	if (!(status & 0x1b))
+		goto err;
+
+	if (status & 0x1)
+		printk (KERN_ERR "Comcerto PCI APBB: Target Abort\n");
+
+	if (status & 0x2)
+		printk (KERN_ERR "Comcerto PCI APBB: Master Abort\n");
+
+	if (status & 0x8)
+		printk (KERN_ERR "Comcerto PCI APBB: Parity error\n");
+
+	if (status & 0x10)
+		printk (KERN_ERR "Comcerto PCI APBB: Retry\n");
+
+	__raw_writel(0x1b, COMCERTO_APBB_INT_STATUS);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+	return IRQ_HANDLED;
+
+  err:
+	return IRQ_NONE;
+#else
+  err:
+	return;
+#endif
+}
+#endif /* defined(CONFIG_COMCERTO_PCI_USE_APBB) */
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+static irqreturn_t comcerto_pci_hmb_irq(int irq, void *dev_id)
+#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+static irqreturn_t comcerto_pci_hmb_irq(int irq, void *dev_id, struct pt_regs *regs)
+#else
+static void comcerto_pci_hmb_irq(int irq, void *dev_id, struct pt_regs *regs)
+#endif
+{
+	u32 status;
+
+	status = __raw_readl(COMCERTO_HMB_STATUS);
+	if (!(status & 0x3))
+		goto err;
+
+	if (status & 0x1)
+		printk (KERN_ERR "Comcerto PCI: HMB Retry/Disconnect\n");
+
+	if (status & 0x2)
+		printk (KERN_ERR "Comcerto PCI: HMB PCI System error\n");
+
+	printk (KERN_INFO "Comcerto PCI: HMB error count %#x\n", status >> 16);	
+
+	__raw_writel(0x3, COMCERTO_HMB_INTACK);
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+	return IRQ_HANDLED;
+
+  err:
+  	return IRQ_NONE;
+#else
+  err:
+	return;
+#endif
+}
+
+#endif /* defined(CONFIG_COMCERTO_PCI_DEBUG) */
+
+
+void __init comcerto_preinit(void)
+{
+	u32 ctl, val;
+
+	/* setup PCI clk */
+	ctl = __raw_readl(COMCERTO_CLK_CLKDIV_CNTRL);
+	ctl &= ~(0x1F << PCI_CLKDIV_RATIO_SHIFT);
+	ctl |= 0x05 << PCI_CLKDIV_RATIO_SHIFT;
+	__raw_writel(ctl, COMCERTO_CLK_CLKDIV_CNTRL);
+	__raw_writel(ctl & ~PCI_CLKDIV_BYPASS, COMCERTO_CLK_CLKDIV_CNTRL);
+
+	/* De-activate PCI reset */
+	__raw_writel(__raw_readl(COMCERTO_BLOCK_RESET_REG) | PCI_RST | HIF_RST , COMCERTO_BLOCK_RESET_REG);
+	/* enable PCI clocking (PCI clock IF + PCI AHB clk) */
+	//__raw_writel(__raw_readl(COMCERTO_CLK_CLK_PWR_DWN) & ~(PCI_CLK_PD | HIF_AHBCLK_PD) , COMCERTO_CLK_CLK_PWR_DWN);
+
+	/* HMDMA setup */
+	__raw_writel(0x04, COMCERTO_HMDMA_LOCKED_TRANSFER_SIZE);
+
+	/* config Host Memory Bridge (hmb) Parameters */
+	__raw_writel(COMCERTO_PCIDMA_SYS_BASE_ADDR1, COMCERTO_HMB_SYS_BASE_ADDR1);
+	__raw_writel(COMCERTO_PCIDMA_SIZE_MASK1, COMCERTO_HMB_SIZE_MASK1);
+
+	__raw_writel(COMCERTO_PCIDMA_SYS_BASE_ADDR2, COMCERTO_HMB_SYS_BASE_ADDR2);
+	__raw_writel(COMCERTO_PCIDMA_SIZE_MASK2, COMCERTO_HMB_SIZE_MASK2);
+
+	/* only 2 ports are allowed to request for PCI bus arbitration
+	   pci device to be bus master */
+	ctl = __raw_readl(COMCERTO_HMB_PCI_ARBITER_CONTROL);
+	__raw_writel(0xff06, COMCERTO_HMB_PCI_ARBITER_CONTROL);	/* priority scheme = round robin, ports 1 & 2 enabled, aging period = 255 */
+	ctl = __raw_readl(COMCERTO_HMB_PCI_ARBITER_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: HMB pci arbiter control: %#x\n", ctl);
+
+	/* read prefetch size = 8 words, programio = HMDMA, timeout = no timeout, timeout cycles = 5 cycles */
+	__raw_writel(0x59, COMCERTO_HMB_MODE_CONTROL);	
+	ctl = __raw_readl(COMCERTO_HMB_MODE_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: HMB mode control: %#x\n", ctl);
+
+	__raw_writel(APBB_CTRL_MEMIO | APBB_CTRL_LATTMR | APBB_CTRL_REQLAST, COMCERTO_APBB_CONTROL);
+
+	/* clear all error bits */
+	__raw_writel(BME_RXTRGABRTIAK | BME_MSTRABRTIAK | BME_SYSERRORIAK | BME_PARERRORIAK | BME_RETRYIAK, COMCERTO_PHI_PCI_IF_STATUS);
+
+	/* Configure Host bus device */
+	if (__comcerto_host_read_config(PCI_VENDOR_ID, 4, &val)) {
+		printk(KERN_ERR "Comcerto PCI: 1- PCI Host device not detected\n");
+	} else if (val != PCI_DEV_VENDOR_ID) {
+		printk(KERN_ERR "Comcerto PCI: PCI Host device detected with val %d \n", val);
+		return;
+	}
+
+	__comcerto_pci_host_init();
+
+	/* enable hmb operation */
+	ctl = __raw_readl(COMCERTO_HMB_STATE_CONTROL);
+	__raw_writel(ctl | 0x01, COMCERTO_HMB_STATE_CONTROL);	/* HMB Mode = enable */
+	ctl = __raw_readl(COMCERTO_HMB_STATE_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: HMB state control: %#x\n", ctl);
+
+	ctl = __raw_readl(COMCERTO_APBB_CONTROL);
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	__raw_writel(ctl | APBB_CTRL_EN, COMCERTO_APBB_CONTROL);	/* APBB Mode = enable */
+#else
+	__raw_writel(ctl & ~APBB_CTRL_EN, COMCERTO_APBB_CONTROL);	/* APBB Mode = disable */
+#endif
+	ctl = __raw_readl(COMCERTO_APBB_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: APBB control: %#x\n", ctl);
+
+#if defined(CONFIG_COMCERTO_PCI_DEBUG)
+	if (request_irq(IRQ_HIF, comcerto_pci_hmb_irq, SA_INTERRUPT, "Comcerto PCI HMB", NULL))
+		__raw_writel(0x0, COMCERTO_HMB_INT_CONTROL);	/* disable all interrupts */
+	else
+		__raw_writel(0x3, COMCERTO_HMB_INT_CONTROL);	/* enable all interrupts */
+
+#if defined(CONFIG_COMCERTO_PCI_USE_APBB)
+	if (request_irq(IRQ_APBB, comcerto_pci_apbb_irq, SA_INTERRUPT, "Comcerto PCI APBB", NULL))
+		__raw_writel(0x00, COMCERTO_APBB_INT_CONTROL);	/* disable all interrupts */
+	else
+		__raw_writel(0x1b, COMCERTO_APBB_INT_CONTROL);	/* enable all interrupts */
+#endif
+
+#else
+	__raw_writel(0x0, COMCERTO_HMB_INT_CONTROL);	/* disable all interrupts */
+	__raw_writel(0x00, COMCERTO_APBB_INT_CONTROL);	/* disable all interrupts */
+#endif
+
+	ctl = __raw_readl(COMCERTO_HMB_INT_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: HMB interrupt control: %#x\n", ctl);
+
+	ctl = __raw_readl(COMCERTO_APBB_INT_CONTROL);
+	printk(KERN_DEBUG "Comcerto PCI: APBB interrupt control: %#x\n", ctl);
+}
+
+void __init comcerto_postinit(void)
+{
+
+}
